Find reasonable transistor sizes for the folded-cascode opamp shown in the provided circuit image to satisfy the following design parameters. Also find the opamp's unity-gain frequency (without feedback) and slew rate, both without and with the clamp transistors.
- Assume the process parameters for the $0.18-\mu \mathrm{m}$ process in Table 1.5, a single $1.8-\mathrm{V}$ power supply, and limit the current dissipation of the opamp to 0.4 mA .
- Set the ratio of the current in the input transistors to that of the cascode transistors to be $4: 1$. Also, set the bias current of $\mathrm{Q}_{11}$ to be $1 / 10$ th that of $\mathrm{Q}_3$ (or $\mathrm{Q}_4$ ) such that its current can be ignored in the power dissipation calculation.
- The maximum transistor width should be $180 \mu \mathrm{~m}$ and channel lengths of $0.4 \mu \mathrm{~m}$ should be used in all transistors.
- All transistors should have effective gate-source voltages of around 0.24 V except for the input transistors, whose widths should be set to the maximum value of $180 \mu \mathrm{~m}$. Also, round all transistor widths to the closest multiple of $2 \mu \mathrm{~m}$, keeping in mind that if a larger transistor is to be matched to a smaller one, the larger transistor should be built as a parallel combination of smaller transistors.
- Finally, assume the load capacitance is given by $\mathrm{C}_{\mathrm{L}}=2.5 \mathrm{pF}$.